Embodiments of the present invention relate generally to a method and system for implementing polarity for a single chip.
High-speed digital communication networks over copper and optical fiber are used in many network communication and digital storage applications. Ethernet and Fiber Channels are two widely used communication protocols that continue to evolve in response to the increasing need for higher bandwidth in digital communication systems.
The Open Systems Interconnection (alternatively referred to as the “OSI”) model (ISO standard) was developed to establish standardization for linking heterogeneous computer and communication systems. The OSI model includes seven distinct functional layers including Layer 7: an application layer; Layer 6: a presentation layer; Layer 5: a session layer; Layer 4: a transport layer; Layer 3: a network layer; Layer 2: a data link layer; and Layer 1: a physical layer. Each OSI layer is responsible for establishing what is to be done at that layer of the network but not how to implement it.
Layers 1 to 4 handle network control, and data transmission and reception. Layers 5 to 7 handle application issues. It is contemplated that specific functions of each layer may vary to a certain extent, depending on the exact requirements of a given protocol to be implemented for that layer. For example, the Ethernet protocol provides collision detection and carrier sensing in the physical layer.
The physical layer (i.e., Layer 1) is responsible for handling all electrical, optical, and mechanical requirements for interfacing to the communication media. The physical layer provides encoding and decoding, synchronization, clock data recovery, and transmission and reception of bit streams. Typically, high-speed electrical or optical transceivers are the hardware elements used to implement such layer.
As data rate and bandwidth requirements increase, 10 Gigabit data transmission rates are being developed and implemented in high-speed networks. Pressure exists to develop a 10 Gigabit physical layer for high-speed serial applications. Transceivers for 10 G applications are needed for the 10 G physical layer. The specification IEEE P802.3ae draft 5 describes the physical layer requirements for 10 Gigabit applications and is incorporated herein by reference in its entirety.
An optical-based transceiver, for example, includes various functional components such as clock data recovery, clock multiplication, serialization/deserialization, encoding/decoding, electrical/optical conversion, descrambling, media access control, controlling, and data storage. Many of the functional components are often implemented in separate IC chips.
It is currently known that transceivers may have a different polarity from the devices or upper level systems with which they are associated (alternatively referred to as “associated devices”). Such different polarities must be accommodated. Some solutions have included inserting one or more chips between the transceiver and the associated devices (or software) to re-configure the polarity. It is contemplated that inserting such a chip may affect production cost and time. Furthermore, such chips may not work correctly, adversely affecting the communication between the transceiver and the associated devices.
Another solution involves making at least two versions of the transceiver, a first version having one polarity, and a second version having the opposite polarity. It is contemplated that this solution is susceptible to error, in that the wrong version of the transceiver may be used, adversely affecting communication between the transceiver and the associated devices.
A further solution involves the crossing of signal paths to achieve correct polarity. This solution, however, results in signal degradation.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.